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description intended for analog and digital satellite receivers, the lnb (low noise block) converter regulator is a monolithic linear and switching voltage regulator, specifically designed to provide power and interface signals to an lnb downconverter, via coaxial cable. the device uses a 2-wire bidirectional serial interface, compatible with the i 2 c (inter-c bus) standard, that operates up to 400 khz. the a8285 is supplied in a 16-lead plastic power soic with internally fused leads for thermal dissipation. the A8287 is supplied in a 24-lead plastic power soic with internally fused leads. both devices are also available in lead (pb) free versions, with 100% matte tine leadframe plating. a8285-ds, rev. f features and benefits ? lnb selection and standby function ? provides up to 500 ma load current ? two-wire serial i 2 c interface ? built-in tone oscillator, factory-trimmed to 22 khz; facilitates diseqc? 2.0 encoding ? auxiliary modulation input ? 22 khz tone detector facilitates diseqc? decoding (A8287 only) ? tracking switch-mode power converter for lowest dissipation ? lnb overcurrent protection and diagnostics ? internal overtemperature protection ? lnb voltages (16 possible levels) compatible with all common standards lnb supply and control voltage regulator packages functional block diagram a8285 and A8287 16-pin soic (a8285) 24-pin soic (A8287) 22 khz tone detector internal regulator boost converter charge pump clock divider 22 khz to n e generator output voltage select fault monitor overcurrent tsd undervoltage vreg boost feedback 33 h 33 f extm v in sda scl add irq 100 mv vin lx 100 nf vcp boost osc in disable 100 nf lnb 220 6.8 nf 33 h 220 nf 1.5 f tcap tout tdi 10 nf v dd tdo v dd osc overcurrent vpump 220 nf overcurrent 15 100 f 100 nf c10 c1 l1 d1 c5 c2 c4 c3 r3 r4 r5 r6 c9 r2 c8 d2 c6 c7 l2 r1 tracking regulator gm
lnb supply and control voltage regulator a8285 and A8287 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit load supply voltage v in 16 v output current i out output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction tempera- ture of +150c internally limited ? output voltage ? lnb, boost ?0.3 to 28 v tout ?0.3 to 22 v logic input ? extm ?0.3 to 5 v other ?0.3 to 7 v logic output ? ?0.3 to 7 v package power dissipation ? see power dis sipation information in the application information section ?? operating temperature ambient t a ?20 to 85 oc junction t j ?20 to 150 oc storage t s ?55 to 150 oc part number pb-free package description a8285slb ? 16-pin soic tone detect not provided a8285slb-t yes 16-pin soic tone detect not provided A8287slb ? 24-pin soic all features A8287slb-t yes 24-pin soic all features selection guide
lnb supply and control voltage regulator a8285 and A8287 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com id characteristics suggested manufacturer c1 33 f, 25 v, esr < 200 m , i ripple > 350 ma nichicon, part number uhc1e330met c2, c5,c10 100 nf, 50 v, x5r or x7r c4 100 f, 35 v, esr < 75 m , i ripple > 800 ma nichicon, part number uhc1v101mpt c3,c6 220 nf, 50 v, x5r or x7r c7 1.5 f, 50 v, x5r or x7r c8 6.8 nf, 50 v; y5v, x5r, or x7r c9 10 nf (maximum), 50 v; y5v, x5r, or x7r r1 15 ? , 1%, c w r2 220 ? , 1%, 2 w r3-r6 value determined by v dd , bus capacitance. etc. l1 33 h, i dc > 1.3 a tdk, part number tsl0808-330k1r4 l2 33 h, i dc > 0.5 a tdk, part number tsl0808-330k1r4 d1 1 a, 35 v or 40 v, schottky diode various, part number 1n5819; sanken, part number aw04 d2 1 a, 100 v, 1n4002 tone detector and leads tdi and tdo are not provided in 16-pin package (a8285).
lnb supply and control voltage regulator a8285 and A8287 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. max. units set-point accuracy, load and line regulation v o1 relative to target voltage selected, with: i load = 0 to 500 ma -4.5 0 4.5 % supply current i cc enb = low, lnb output disabled ?? 7ma i ccen enb = high, lnb output enabled, i load = 0ma ?? 15 ma boost switch-on resistance r dsboost t j = 25 c, i load = 500ma ? 400 500 m ? switching frequency fo ? 320 352 384 khz switch current limit ? v in = 12 v 2.0 3 4.0 a linear regulator voltage drop ? v reg v boost ? v lnb , no tone signal, i load = 500 ma 400 600 800 mv slew rate current on tcap i cap charging ?12.5 ?10 ?7.5 a discharging 7.5 10 12.5 a output voltage slew period t slew v lnb = 13 to 18 v, tcap = 6.8 nf, i load = 500 ma ? 500 ? s output reverse current i or enb = low, v lnb = 28 v with c4 fully charged ? 15ma ripple and noise on lnb output v rn see notes 1 and 2 ?? 50 mv pp protection circuitry overcurrent limit i lim high limit low limit 550 400 700 500 850 600 ma ma overcurrent disable time t dis ? 1.2 ? 1.7 ms v in undervoltage threshold uv off guaranteed turn-off 8.65 9.15 9.65 v v in turn-on threshold uv on guaranteed turn-on 8.75 9.25 9.75 v power-not-good flag set png set ? 77 85 93 %v lnb power-not-good flag reset png reset ? 82 90 98 %v lnb thermal shutdown threshold t j see note 1 ? 165 ? c thermal shutdown hysteresis ? t j see note 1 ? 20 ? c electrical characteristics at t a = +25c, v in = 10 to 16 v (unless otherwise noted) continued on next page
lnb supply and control voltage regulator a8285 and A8287 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics ( continued ) at t a = +25c, v in = 10 to 16 v (unless otherwise noted) characteristics symbol test conditions min. typ. max. units tone characteristics tone frequency f tone ? 20 22 24 khz tone pull-down current i tone ?304050ma tone turn-on and turn-off delays t del using extm pin ? ? 1 s external tone logic input v ih ?2??v v il ? ? ? 0.8 v input leakage i il ??1?1 a tone detector input amplitude v tdi f in = 22 khz 260 ? 1000 mv tone detector frequency capture f tdi 600 mv pp sinewave 17.6 ? 26.4 khz tone detector input impedance z tdi see note 1 ? 8.6 ? k ? tone detector output voltage v ol tone present, i load = 3 ma ? ? 0.4 v tone detector output leakage i ol tone absent, v o = 7 v ? ? 10 ? a i 2 c interface logic input (sda,scl) low level v il ? ? ? 0.8 v logic input (sda,scl) high level v ih ?2??v input hysteresis v hys ? ? 150 ? mv logic input current i in v in = 0 v to 7 v ?10 <1.0 10 a output voltage (sda, irq) v ol i load = 3 ma ? ? 0.4 v output leakage (sda, irq) i ol v o = 0 v to 7 v ? ? 10 a scl clock frequency f clk ? 0 ? 400 khz output fall time t of v ih to v il ? ? 250 ns bus free time between stop and start t buf see i 2 c interface timing diagram 1.3 ? ? s hold time for start condition t hd:sta see i 2 c interface timing diagram 0.6 ? ? s setup time for start condition t su:sta see i 2 c interface timing diagram 0.6 ? ? s scl low time t low see i 2 c interface timing diagram 1.3 ? ? s scl high time t high see i 2 c interface timing diagram 0.6 ? ? s data setup time t su:dat see note1; i 2 c interface timing diagram 100 ? ? ns data hold time t hd:dat see i 2 c interface timing diagram 0 ? 900 ns setup time for stop condition t su:sto see i 2 c interface timing diagram 0.6 ? ? s continued on next page
lnb supply and control voltage regulator a8285 and A8287 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i 2 c address setting add voltage for address 0001,000 address1 ? 0 ? 0.7 v add voltage for address 0001,001 address2 ? 1.3 ? 1.7 v add voltage for address 0001,010 address3 ? 2.3 ? 2.7 v add voltage for address 0001,011 address4 ? 3.3 ? 5v 1 guaranteed by design. 2 use recommended components and adhere to layout guidelines. electrical characteristics ( continued ) at t a = +25c, v in = 10 to 16 v (unless otherwise noted) characteristics symbol test conditions min. typ. max. units t su:sta t hd:sta t su:dat t hd:dat t buf t su:sto t high t low sda scl i 2 c interface timing diagram
lnb supply and control voltage regulator a8285 and A8287 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boost converter/linear regulator . a current-mode boost converter provides the tracking regulator a supply voltage that tracks the requested lnb output voltage. the converter operates at 16 times the internal tone frequency, 352 khz nominal. the tracking regulator provides minimum power dissipation across the range of output voltages, assuming the input voltage is less than the output voltage, by adjusting the boost pin voltage 600 mv nominal above the lnb output voltage selected. under conditions where the input voltage is greater than the output voltage, the tracking regulator must drop the differential voltage. when operating in this condition, care must be taken to ensure that the safe operating temperature range of the a8285/A8287 is not exceeded. for additional information, see power dissipation in the application information section. note: to conserve power at light loads, the boost converter oper- ates in a pulse-skipping mode. overcurrent protection. the a8285/A8287 is protected against both overcurrent and short circuit conditions by limit- ing the output current to i lim . in the event of an overcurrent, the current limit can be applied indefinitely. alternatively, if the odt feature is enabled, and the fault current appears for longer than the disable time t dis , then the device is turned off. the device can be enabled again via the i 2 c? interface. if the overcurrent is removed before the disable time has elapsed, the device remains functioning. these settings are made in the con- trol register and the status register. charge pump . generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. slew rate control . during either start-up or when the output voltage on the boost pin is being changed, the output voltage rise and fall times can be programmed by an external capacitor located on the tcap pin. note that during start-up, the boost pin is precharged to the input voltage minus a diode drop. as a result, the slew rate control occurs from this point. the value for tcap can be calculated using the following for- mula: tcap = (i cap 8) / ( v/s) where v/s is required slew rate. the smallest value for tcap is 2.2 nf. modulation is unaffected by the choice of tcap. if limiting lnb output voltage rise and fall times is not required, the tcap terminal must have a value of at least a 2.2 nf to minimize output noise. external tone modulation . to improve design flexibility and to allow implementation of proposed lnb remote control standards, the logic modulation input pin extm is provided. the logic signal supplied to this pin creates a 650 mv 250 mv tone signal on the tout pin by controlling a 40 ma current pull-down device through the diseqc? filter. the shape of the tone waveform depends on the filter components used and the lnb/cable capacitance. tone detection . a 22 khz tone envelope detector is provided in the A8287 solution. the detector extracts the tone signal and provides it as an open-collector signal on the tdo pin. the maxi- mum tone out error is 1 tone cycle, and the maximum tone out delay with respect to the input is 1 tone cycle. control register . the main functions of the a8285/A8287 are controlled via the i 2 c interface by writing to the control register. the power-up states for the control functions are all zero. control functions include the following: ? internal tone modulation enable (ent) . when the ent bit is set to 1, the internal tone generator controls a 40 ma pull-down device, thus creating the tone signal after the diseqc? filter in a way identical to the extm scheme. the internal oscillator is factory-trimmed to provide a tone of 22 2 khz. no further adjustment is required. burst coding of the 22 khz tone is accomplished due to the fast response of the serial command and rapid tone response. this allows implementation of the diseqc? 2.0 protocols. ? select output voltage amplitude (vsel0, vsel1, vsel2, vsel3). the lnb output voltage can be programmed to a partic- ular voltage according to the output voltage amplitude selection table shown on the following page. ? enable (enb) . when set to 1, the lnb output is enabled. when reset to 0, the lnb output is disabled. ? overcurrent limit (i lim ) . selects the output overcurrent limit. when set to 0, the limit is 500 ma. when set to 1, the limit is 700 ma. ? overcurrent disable time (odt) . when set to 1, in the event of an overcurrent occuring for a duration exceeding the disable time, the device is turned off. when set to 0, functional description
lnb supply and control voltage regulator a8285 and A8287 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com this feature is disabled and the device is not turned off during an overcurrent. status register . the status of the a8285/A8287 read regis- ter can be interrogated by the system master controller via the i 2 c??compatible interface. status functions include the follow- ing: ? power not good (png) . when the lnb output is enabled, and the lnb output is below 85% of the programmed lnb voltage, the png bit is set. ? disable (dis). provides the status of the lnb output. when set, this indicates that the output is disabled, either intentionally or by a fault. ? thermal shutdown (tsd) . when the junction temperature exceeds the maximum threshold, the thermal shutdown bit is set, which disables the lnb output. dis also is set. ? overcurrent (ocp) . this disables lnb output when an overcurrent appears on the lnb output for a period greater than the odt (odt must be enabled for this feature to take effect). in addition, the dis bit is set. note: if an overcurrent occurs and odt is disabled, the a8285/A8287 will operate in current limit indefininitely and the ocp bit will not be set. ? undervoltage lockout (vuv) . when the input voltage (v in ) drops below the undervoltage threshold, the undervoltage bit vuv is set, disabling the output. when v in is initially applied to the a8285/a8285, the vuv bit is set, indicating that an undervoltage condition has occurred. irq flag . the irq flag is activated when any fault condition occurs, including: thermal shutdown, overcurrent, undervoltage, or the occurrence of a power-up sequence. note that the irq flag is not activated when either (a) the channel is disabled (dis), as it may have been disabled intentionally by the master controller, or (b) if png is active, as the a8285/A8287 may be starting up. fault conditions are stored in the status registers. also note that the irq flag will not activate when an overcurrent occurs and odt is disabled. in this condition, the device operates within i lim . when the irq flag is activated during either of the above fault conditions, and the system master controller addresses the a8285/A8287 with the read/write bit set to 1, then the irq flag is reset once the a8285/A8287 acknowledges the address. when the master controller reads the data and is acknowledged, the status registers are updated. if the fault is removed, the a8285/ A8287 is again ready for operation (being re-enabled via a write command). otherwise, the controller can keep polling the a8285/ A8287 until the fault is removed. when v in , is initially applied to the a8285/a8285, the i 2 c?? compatible interface will not function until the internal logic supply v reg has reached its operating level. once v reg is within tolerance, the vuv bit in the status register is set and the irq is activated to inform the master controller of this condition. (the irq is effectively acting as a power-up flag.) the irq is reset when the a8285/A8287 acknowledges the address. once the master has read the status registers, the vuv bit is reset. the device is then ready for operation. i 2 c??compatible interface . this is a serial interface that uses two bus lines, scl and sda, to access the internal control and status registers of the a8285/A8287. data is exchanged between a microcontroller (master) and the a8285/A8287 (slave). the clock input to scl is generated by the master, while sda functions as either an input or an open drain output, depending on the direction of the data. vsel3 vsel2 vsel1 vsel0 lnb (v) 0 0 0 0 12.709 0 0 0 1 13.042 0 0 1 0 13.375 0 0 1 1 13.709 0 1 0 0 14.042 0 1 0 1 14.375 0 1 1 0 14.709 0 1 1 1 15.042 1 0 0 0 18.042 1 0 0 1 18.375 1 0 1 0 18.709 1 0 1 1 19.042 1 1 0 0 19.375 1 1 0 1 19.709 1 1 1 0 20.042 1 1 1 1 20.375 output voltage amplitude selection table
lnb supply and control voltage regulator a8285 and A8287 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing considerations the control sequence of the communication through the i 2 c?- compatible interface is composed of several steps in sequence: 1. start condition . defined by a negative edge on the sda line, while scl is high. 2. address cycle . 7 bits of address, plus 1 bit to indicate read (1) or write (0), and an acknowledge bit. the first five bits of the address are fixed as: 00010 . the four optional addresses, defined by the remaining two bits, are selected by the add input. the address is transmitted msb first. 3. data cycles . 8 bits of data followed by an acknowledge bit. multiple data bytes can be read. data is transmitted msb first. 4. stop condition . defined by a positive edge on the sda line, while scl is high. except to indicate a start or stop condition, sda must be stable while the clock is high. sda can only be changed while scl is low. it is possible for the start or stop condition to occur at any time during a data transfer. the a8285/A8287 always responds by resetting the data transfer sequence. the read/write bit is used to determine the data transfer direc- tion. if the read/write bit is high, the master reads one or more bytes from the a8285/A8287. if the read/write bit is low, the master writes one byte to the a8285/A8287. note that multiple writes are not permitted. all write operations must be preceded with the address. the acknowledge bit has two functions. it is used by the master to determine if the slave device is responding to its address and data, and it is used by the slave when the master is reading data back from the slave. when the a8285/A8287 decodes the 7-bit address field as a valid address, it responds by pulling sda low during the ninth clock cycle. during a data write from the master, the a8285/A8287 also pulls sda low during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received. in both cases, the master device must release the application information 1 2 3 4 5 6 7 8 9 0 0 0 1 0 a1 a0 0 ak ak d6 d5 d4 d3 d2 d1 d0 d7 control data address start w stop sda scl acknowledge from lnbr acknowledge from lnbr 0 0 0 1 0 a1 a0 1 ak d6 d5 d4 d3 d2 d1 d0 d7 nak status data address start r stop 1 2 3 4 5 6 7 8 9 sda scl no acknowledge from maste r acknowledge from lnbr 0 0 0 1 0 a1 a0 1 ak d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 ak nak status data address start r stop status data 1 2 3 4 5 6 7 8 9 sda scl acknowledge from master acknowledge from lnbr no acknowledge from maste r writing to the register reading one byte from the register reading multiple bytes from the register
lnb supply and control voltage regulator a8285 and A8287 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sda line before the ninth clock cycle, in order to allow this handshaking to occur. during a data read, the a8285/A8287 acknowledges the address in the same way as in the data write sequence, and then retains control of the sda line and send the data to the master. on completion of the eight data bits, the a8285/A8287 releases the sda line before the ninth clock cycle, in order to allow the master to acknowledge the data. if the master holds the sda line low during this acknowledge bit, the a8285/A8287 responds by sending another data byte to the master. data bytes continue to be sent to the master until the master releases the sda line during the acknowledge bit. when this is detected, the a8285/A8287 stops sending data and waits for a stop signal. interrupt request . the a8285/A8287 also provides an inter- rupt request pin irq, which is an open-drain, active-low output. this output may be connected to a common irq line with a suitable external pull-up and can be used with other i 2 c devices to request attention from the master controller. the irq output becomes active when either the a8285/A8287 first recognizes a fault condition, or at power-on when the main supply v in and the internal logic supply v reg reach the correct operating condi- tions. it is only reset to inactive when the i 2 c master addresses the a8285/A8287 with the read/write bit set (causing a read). fault conditions are indicated by the tsd, vuv, and ocp bits in the status register (see description of ocp for conditions of use). the dis and png bits do not cause an interrupt. when the master recognizes an interrupt, it addresses all slaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting attention. the a8285/ A8287 latches all conditions in the status register until the completion of the data read. the action at the resampling point is further defined in the description for each of the status bits. the bits in the status reg- ister are defined such that the all-zero condition indicates that the a8285/A8287 is fully active with no fault conditions. when v in is initially applied, the i 2 c interface does not respond to any requests until the internal logic supply v reg has reached its operating level. once v reg has reached this point, the irq output goes active, and the vuv bit is set. after the a8285/ A8287 acknowledges the address, the irq flag is reset. once the master reads the status registers, the registers are updated with the vuv reset. control register (write register). all main functions of the a8285/A8287 are controlled through the i 2 c interface via the 8-bit control register. this register allows selection of the output voltage and current limit, enabling and disabling the lnb output, and switching the 22 khz tone on and off. the power-up state is 0 for all of the control functions. bit 0 (vsel0), bit 1 (vsel1), and bit 2 (vsel2) . these provide incremental control over the voltage on the lnb output. the available voltages provide the necessary levels for all the common standards plus the ability to add line compensation in increments of 333 mv. the voltage levels are defined in the out- put voltage amplitude selection table. bit 3 (vsel3) . switches between the low-level and high-level output voltages on the lnb output. a value of 0 selects the low level voltage and a value of 1 selects the high level. the low- level center voltage is 12.709 v nominal, and the high level is 18.042 v nominal. these may be increased, in increments of 333 mv, by using the vsel2, vsel1, and vsel0 control register bits. bit 4 (odt) . when set to 1, enables the odt feature (disables the a8285/A8287 if the overcurrent disable time is exceeded during an overcurrent condition on the output). when set to 0, the odt feature is disabled. 0 0 0 1 0 a1 a0 1 ak d6 d5 d4 d3 d2 d1 d0 d7 nak status data address start r stop 1 2 3 4 5 6 7 8 9 sda scl irq fault event reload status register reading the register after an interrupt
lnb supply and control voltage regulator a8285 and A8287 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com bit 5 (enb) . when set to 1, enables the lnb output. when set to 0, the lnb output is disabled. bit 6 (i lim ) . selects the i lim level. when set to 0, the lower limit (typically 500 ma) is selected. when set to 1, the higher limit (typically 700 ma), is selected. bit 7 (ent) . when set to 1, enables modulation of the lnb out- put with the the internal 22 khz tone. since the i 2 c interface is compatible with the 400 khz transfer speed, this bit may be used to encode diseqc? 2.0 tone bursts for communication with the lnb or switcher at the far end of the coaxial cable. status register (i 2 c read register) . the main fault condi- tions: overcurrent, undervoltage, and overtemperature, are all indicated by setting the relevant bit in the status register. in all fault cases, once the bit is set it is not reset until the a8285/ A8287 is read by the i 2 c master. the current status of the lnb output is also indicated by dis. dis and png are the only bits that may be reset without an i 2 c read sequence. the normal sequence of the master in a fault condition is to detect the fault by reading the status register, then rereading the status register until the status bit is reset, indicating the fault condition has been reset. the fault may be detected by: continuously polling, responding to an interrupt request (irq), or detecting a fault condition exter- nally and performing a diagnostic poll of all slave devices. note that the fully operational condition of the status register is all 0s. this simplifies checking of the status byte. bit 0 (tsd) . a 1 indicates that the a8285/A8287 has detected an overtemperature condition and has disabled the lnb output. dis is set and the a8285/A8287 does not re-enable the output until so instructed by writing the relevant bit into the control register. the status of the overtemperature condition is sampled on the ris- ing edge of the ninth clock pulse in the data read sequence. if the condition is no longer present, then the tsd bit is reset, allowing the master to re-enable the lnb output if required. if the condi- tion is still present, then the tsd bit remains at 1. bit 1 (ocp) overcurrent . if the a8285/A8287 detects an over- current condition for greater than the detection time, and if odt is enabled, the lnb output is then disabled. also, the ocp bit is set to indicate that an overcurrent has occurred, and the dis bit is set. the status register is updated on the rising edge of the ninth clock pulse. the ocp bit is reset in all cases, allowing the master to re-enable the lnb output. if the overcurrent timer is not enabled, the a8285/A8287 operates in current limit indefinitely, and the ocp bit is not set. bit 2 and 3. reserved. bit 4 (png) power not good . set to 1 when the lnb output is enabled and the lnb output volts are below 85% of the pro- grammed lnb voltage. the png is reset when the lnb volts are within 90% of the programmed lnb voltage. bit 5 (dis) lnb output disabled . dis is used to indicate the current condition of the lnb output. at power-on, or if a fault condition occurs, the disable bit is set. having this bit change to 1 does not cause the irq to activate because the lnb output may be disabled intentionally by the i 2 c master. this bit also is reset at the end of a write sequence, if the lnb output is enabled. bit 6. reserved. bit 7 (vuv) undervoltage lockout. set to 1 to indicate that the a8285/A8287 has detected that the input supply v in is, or has been, below the minimum level and that an undervoltage lockout has occurred, which has disabled the lnb output. bit 5 also is set, and the a8285/A8287 does not re-enable the output until so instructed (by having the relevant bit written into the control reg- ister). the status of the undervoltage condition is sampled on the rising edge of the ninth clock pulse in the data read sequence. if the condition is no longer present, the vuv bit is reset, allowing the master to re-enable the lnb output if required. if the condi- tion is still present, the vuv bit remains set to 1. bit name function 0 vsel0 see output voltage amplitude selection table 1 vsel1 2 vsel2 3 vsel3 0: lnbx = low range 1: lnbx = high range 4 odt 0: overcurrent disable time off 1: overcurrent disable time on 5 enb 0: disable lnb output 1: enable lnb output 6 ilim 0: overcurrent limit = 500ma 1: overcurrent limit = 700ma 7 ent 0: disable tone 1: enable 22khz internal tone control (write) register table
lnb supply and control voltage regulator a8285 and A8287 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com power dissipation to ensure that the device operates within the safe operating temperature range, several checks should be performed. an approximate operating junction temperature can be determined by estimating the power losses and the thermal impedance character- istics of the printed circuit board solution. to do so, perform the following procedure: 1. estimate the maximum ambient temperature (t a ). 2. define the maximum running junction temperature (t j )of a8285/A8287. note that the absolute maximum junction tem- perature should never exceed 150oc. 3. determine worst case power dissipation: (a) estimate the duty cycle d: d = 1 ? [v in / (v out + v d + v reg )] where: v d is the voltage drop of the boost diode, and v reg can be taken from the specification table. (b) estimate the peak current in boost stage i pk : i pk = v out [ i load / (0.89 v in )] (c) estimate boost r ds (r dsboost ) at maximum running junc- tion temperature. r dsboost is a function of junction temperature bit name function 0 tsd thermal shutdown 1 ocp overcurrent 2 reserved 3 reserved 4 png power not good 5 dis lnb output disabled 6 reserved 7 vuv v in undervoltage status (read) register table and it rises by 2.7 m /oc with respect to the specified figure, r dsboost(25oc) , when t j equals 25oc. actual r dsboost = r dsboost(25oc) + [(t j ? 25) 2.7 m ] (d) determine losses in each block p tot ; based on the relative value of v in , perform either (i) or (ii): (i) when v in < v out + v d + v reg . note that worst case dis- sipation occurs at minimum input voltage. p tot = pd_rds + pd_sw + pd_control + pd_lin where pd_rds = i 2 pk r dsboost d pd_control = 15 ma v in pd_lin = v reg i load and pd_sw (switching losses estimate); worst case = 70 mw. (ii) when v in > v out + v d + v reg . note that worst case dis- sipation in this case occurs at maximum input voltage. p tot = pd_control + pd_lin where: pd_control = 15 ma v in pd_lin = (v in ? v d ? v out ) i load step 4. determine the thermal impedance required in the solu- tion: r ?ja = (t j ? t a ) / p tot the r ?ja for one or two layer pcbs can be estimated from the r ?ja vs. area charts on the following page. note: for maximum effectiveness, the pcb area underneath the ic should be filled copper and connected to pins 4 and 13 for a8285, and pins 6, 7, 18, and 19 for A8287. where a pcb with two or more layers is used, apply thermal vias, placing them adja- cent to each of the above pins, and underneath the ic.
lnb supply and control voltage regulator a8285 and A8287 13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com example. given: v in = 12 v v out = 18 v i load = 500 ma two-layer pcb. maximum ambient temperature = 70 oc, maximum allowed junction temperature= 110 oc assume: v d = 0.4 v and select v reg = 0.7 v d = 1 ? (12 / (18 + 0.4 + 0.7) = 0.37 i pk = 18 0.5 / (0.89 12) = 843 ma r dsboost = 0.5 + (110 ? 25) 2.7 m = 730 m worst case losses can now be estimated: pd_rds = 0.843 2 0.73 0.37 = 192 mw pd_sw = 70 mw pd_control = 15 ma v in = 180 mw pd_lin = 0.7 0.5 = 350 mw and therefore p tot = 0.192 + 0.07 + 0.18 + 0.35 = 0.792 w the thermal resistance required is: (110 ? 70) / 0.792 = 50.5oc/w note: for the case of the A8287, the area of copper required on each layer is approximately 1.2 in 2 . layout considerations recommended placement of critical components and tracking for the A8287 is shown in the pcb layout digagram on the follow- ing page. it is recommended that the ground plane be separated into two areas, referred to as switcher and control, on each layer using a ground plane. with respect to the input connections, vin and 0v, the two ground plane areas are isolated as shown by the dotted line and the ground plane areas are connected together at pins 6, 7, 18, and 19. this configuration minimizes the effects of the noise produced by the switcher on the noise-sensitive sections of the circuit. power-related tracking from input to l1, lnb (pin 17) to l2 then output, lx (pin 20) to d1 and l1, vboost (pin 23) to c4 and d1 should be as short and wide as possible. power components such as the boost diode d1, inductor l1, and input/ output capacitors c1, c9, and c4, should be located as close as possible to the ic. the diseqc inductor l2 should be located as far away from the boost inductor l1 to prevent potential magnetic crosstalk. the filter capacitor (vreg), charge pump capacitor (vcp), ac coupling tone detect capacitor (tdi), tone pull-down resis- tor (tout), and lnb output capacitor/protection diode (lnb) should be located directly next to the appropriate pin. where a pcb with two or more layers is used, it is recommended that four thermal vias be deployed as shown in the pcb layout diagram. note that adding additional vias does not enhance the thermal characteristics. 40 50 60 70 80 90 100 01234 area (in 2 ) thermal resistance ( 0 c/w) one side copper two side copper 40 50 60 70 80 01234 area (in 2 ) thermal resistance ( 0 c/w) one side copper two side copper r ?ja vs. area charts a8285, 16-pin soic A8287, 24-pin soic thermal resistance (oc /w) thermal resistance (oc /w) area (in. 2 ) area (in. 2 )
lnb supply and control voltage regulator a8285 and A8287 14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com note that to add additional connec- tions, e.g. scl, sda, irq, vin, extm, add, tdo, and tdi, some modifications to the control ground plane will be necessary. refer to functional block diagram for circuit connections. pcb layout diagram power-on reset i 2 c sequence adr read a a r s t s p adr write a a w s t s p master responds to irq reads status vuv = 1 master writes enables output sda irq vuv reset v reg v in read n vuv = 0 output thermal via cut in 0v plane + + c1 c5 c2 c8 c7 c6 c4 l1 l2 r1 + d1 + d2 13 15 14 18 17 16 22 21 20 19 24 23 vin (input) tracking 0v pla ne c3 control 0v control 0v control 0v switch er 0v 1 12 4 3 2 7 6 5 10 9 8 11 c9 0v 0v
lnb supply and control voltage regulator a8285 and A8287 15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com response to overtemperature fault condition using multiple byte read overtemperature and overcurrent i 2 c sequences response to overcurrent fault condition using single byte read adr read a n r s t s p adr read a n r s t s p adr write a a w s t s p master responds to irq reads status ocp = 1 dis = 1 master polls reads status ocp = 0 dis = 0 master writes re-enables lnb output sda irq ocp reset i lnb v lnb lnb ou t pu t di sa bl e d lnb output enable d adr read a a r s t s p adr write a a w s t s p master responds to irq reads status continuously tsd = 1 dis = 1 master writes re-enables lnb output read a read a read a read n tsd reset tsd = 0 dis = 1 sda irq t jmax t jmax - ? t j t j lnb ouput enabled lnb output disabled overtemperature
lnb supply and control voltage regulator a8285 and A8287 16 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin name pin description A8287slb soic-24 a8285slb soic-16 scl i 2 c clock input 1 1 sda i 2 c data input/output 2 2 irq interrupt request 3 3 gnd ground 4,5,6,7 4 vreg analog supply 8 5 vin supply input voltage 9 6 extm external modulation input 10 7 add address select 11 8 tdo tone detect out 12 - tdi tone detect input 13 - nc no connection 14 9 tcap capacitor for setting the rise and fall time of the lnb output 15 10 tout tone generation 16 11 lnb output voltage to lnb 17 12 gnd ground 18,19 13 lx inductor drive point 20 14 gnd ground 21,22 - boost tracking supply voltage to linear regulator 23 15 vcp gate supply voltage 24 16 terminal list table
lnb supply and control voltage regulator a8285 and A8287 17 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a8285slb 16-pin batwing soic notes: 1. exact body and lead con guration at vendor?s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 49 devices or add ?tr? to part number for tape and reel. .606 .598 15.39 15.19 .299 .291 7.59 7.39 .414 .398 10.52 10.11 .020 .014 0.51 0.36 .026 ref 0.66 .050 bsc 1.27 .012 .004 0.30 0.10 .104 .096 2.64 2.44 .040 .020 1.02 0.51 .011 .009 0.28 0.23 8o 0o dimensions in inches metric dimensions (mm) in brackets, for reference only 2 17 6 24 19 18 A8287slb 24-pin batwing soic .406 .398 10.31 10.11 .299 .291 7.59 7.39 .414 .398 10.52 10.11 .020 .014 0.51 0.36 .026 ref 0.66 .050 bsc 1.27 .012 .004 0.30 0.10 .104 .096 2.64 2.44 .040 .020 1.02 0.51 .011 .009 0.28 0.23 8o 0o dimensions in inches metric dimensions (mm) in brackets, for reference only 2 1 16 leads 4 and 13 are connected inside the device package. leads 6, 7, 18 and 19 are connected intside the device package.
lnb supply and control voltage regulator a8285 and A8287 18 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes no re- spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. i 2 c? is a trademark of philips semiconductors. diseqc? is a registered trademark of eutelsat s.a. copyright?2003-2013 allegromicrosystems, llc

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